PDENG on high-speed error correcting codes and signal shaping

Fibre optics are critical infrastructure for society because they carry nearly all the global Internet traffic. Over the last years, we have seen an explosive increase of data rates in fibre optics. For instance, in the short-haul domain, the traffic between data centers experienced a 400% growth from 2016 to 2021. This growth is a challenge not only to the technology demands but also to energy consumption. A single state-of-the-art optical transponder can reach a total power consumption of 700W. Applying Soft-Decision Forward Error Correction (SD-FEC) decoders would be superior in such multi-gigabit per second systems, but their power consumption is up to two orders of magnitude higher than Hard-Decision Forward Error Correction (HD-FEC) decoders. However, choosing the technology with better energy efficiency comes with a cost: HD-FEC decoders entail a significant performance loss, which will prevent the use of HD-FEC decoders in ultra-high-throughput fiber optics. More broadly, such drawbacks will also make HD-FEC decoders impractical for beyond 5G mobile communications and future wireless local area network (WiFi-like) standards. In order not to increase power consumption of future high-throughput communication systems further, the error correction algorithms need to be replaced with completely new approaches.

Recently proposed hybrid FEC (HY-FEC) systems, e.g., SABM, iBDD-SR, SABM-SR, iBDD-CR, etc., tackle the challenge above by combining flavors from high-performance SD-FEC and from low-power HD-FEC [1-4]. At an algorithm level, HY-FEC is able to close the performance gap between SD-FEC and HD-FEC, but with at least one order of magnitude lower energy consumption than that of SD-FEC. Furthermore, next-generation communication systems use high-order constellations. Approximately-realized constellation shaping (SH) techniques, applied to high-order constellations, have been shown to provide higher data rates than uniform signaling approaches, with low-complexity (LC) [5-7]. Investigating the performance of LC-SH / HY-FEC combinations is the core of this project, and a corresponding FPGA implementation is the key objective of this position.